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<a href="#pub-attribs">Data Fields</a>  </div>
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<div class="title">RCC_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s.html">CMSIS</a> &raquo; <a class="el" href="group__wb32l003.html">Wb32l003</a> &raquo; <a class="el" href="group___device___peripheral__peripherals.html">Device_Peripheral_peripherals</a></div></div>  </div>
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Data Fields</h2></td></tr>
<tr class="memitem:a5948f85dc192aaad63fc2394efdea69d"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_r_c_c___type_def.html#a5948f85dc192aaad63fc2394efdea69d">HCLKDIV</a></td></tr>
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<tr class="memitem:a71e10dd659b43a3ca87659be482140fd"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_r_c_c___type_def.html#a71e10dd659b43a3ca87659be482140fd">LSITC</a></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
<a id="a5948f85dc192aaad63fc2394efdea69d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a5948f85dc192aaad63fc2394efdea69d">&#9670;&nbsp;</a></span>HCLKDIV</h2>

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<p>RCC AHB clock prescale register, Address offset: 0x000 </p>

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</div>
<a id="a10b17bc9cf8a196759576a12c6ff7cc1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a10b17bc9cf8a196759576a12c6ff7cc1">&#9670;&nbsp;</a></span>HCLKEN</h2>

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<p>RCC AHB peripheral model clock enable register, Address offset: 0x008 </p>

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</div>
<a id="a504ebffda447e3765b72102db68ad761"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a504ebffda447e3765b72102db68ad761">&#9670;&nbsp;</a></span>HSECR</h2>

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<p>RCC hse control register, Address offset: 0x02C </p>

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</div>
<a id="a4d1b76d2c1f46d75ea6abfc2fedf0bc7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a4d1b76d2c1f46d75ea6abfc2fedf0bc7">&#9670;&nbsp;</a></span>HSICR</h2>

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<p>RCC hsi control register, Address offset: 0x028 </p>

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</div>
<a id="af9f51f87cc32d9168424580875f16118"></a>
<h2 class="memtitle"><span class="permalink"><a href="#af9f51f87cc32d9168424580875f16118">&#9670;&nbsp;</a></span>HSISTABCR</h2>

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          <td class="memname">__IOM uint32_t HSISTABCR</td>
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<p>RCC register, Address offset: 0x390 </p>

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</div>
<a id="a3fc4510fe7e5f6ccc36f48fac0d58ccf"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a3fc4510fe7e5f6ccc36f48fac0d58ccf">&#9670;&nbsp;</a></span>HSITC</h2>

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<p>RCC Internal high speed OSC control register 2, Address offset: 0x394 </p>

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</div>
<a id="a21952e83248e6f96e5b86bbfc4d2eb23"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a21952e83248e6f96e5b86bbfc4d2eb23">&#9670;&nbsp;</a></span>IRQLATENCY</h2>

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        <tr>
          <td class="memname">__IOM uint32_t IRQLATENCY</td>
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<p>RCC m0 irq delay register, Address offset: 0x038 </p>

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</div>
<a id="a58ca5a268ed420eefa9998d32a96729e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a58ca5a268ed420eefa9998d32a96729e">&#9670;&nbsp;</a></span>LSECR</h2>

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          <td class="memname">__IOM uint32_t LSECR</td>
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<p>RCC lse control register, Address offset: 0x034 </p>

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</div>
<a id="ac9ea4c5133cab4fdbb980afc8300a0c3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ac9ea4c5133cab4fdbb980afc8300a0c3">&#9670;&nbsp;</a></span>LSICR</h2>

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          <td class="memname">__IOM uint32_t LSICR</td>
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<p>RCC lsi control register, Address offset: 0x030 </p>

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</div>
<a id="a71e10dd659b43a3ca87659be482140fd"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a71e10dd659b43a3ca87659be482140fd">&#9670;&nbsp;</a></span>LSITC</h2>

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<p>RCC register, Address offset: 0x398 </p>

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</div>
<a id="a1fa98e220d45f27269f94800e78b6798"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a1fa98e220d45f27269f94800e78b6798">&#9670;&nbsp;</a></span>MCOCR</h2>

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<p>RCC clock output control register, Address offset: 0x010 </p>

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<a id="aa3db16a136f52fb612c3273d119b4609"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aa3db16a136f52fb612c3273d119b4609">&#9670;&nbsp;</a></span>PCLKDIV</h2>

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<p>RCC apb clock prescale register, Address offset: 0x004 </p>

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<a id="a7536bfedbfe81b033aaa4233b76adf50"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a7536bfedbfe81b033aaa4233b76adf50">&#9670;&nbsp;</a></span>PCLKEN</h2>

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<p>RCC apb peripheral model clock enable register, Address offset: 0x00C </p>

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</div>
<a id="a4f1ce3f84aad487c0d804b07d1f32149"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a4f1ce3f84aad487c0d804b07d1f32149">&#9670;&nbsp;</a></span>PERIRST</h2>

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<p>RCC peripheral model control register, Address offset: 0x044 </p>

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</div>
<a id="affe1e3b2698318444ab40110f094a385"></a>
<h2 class="memtitle"><span class="permalink"><a href="#affe1e3b2698318444ab40110f094a385">&#9670;&nbsp;</a></span>RESERVED0</h2>

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          <td class="memname">__IM uint32_t RESERVED0</td>
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<p>Address offset: 0x014 </p>

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<a id="ad651b9738c795d6ef0067b0bf5d8ca7a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ad651b9738c795d6ef0067b0bf5d8ca7a">&#9670;&nbsp;</a></span>RESERVED1</h2>

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<p>Address offset: 0x04C </p>

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<a id="acb5bf8871969abe7f692d8ad13a1324b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#acb5bf8871969abe7f692d8ad13a1324b">&#9670;&nbsp;</a></span>RESERVED2</h2>

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<p>Address offset: 0x064 </p>

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<a id="a1653aada293cdb48c5fe744000394f41"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a1653aada293cdb48c5fe744000394f41">&#9670;&nbsp;</a></span>RSTCR</h2>

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<p>RCC system reset control register, Address offset: 0x018 </p>

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<a id="abed3177ba5248ce1d88a8e5b1b0975ce"></a>
<h2 class="memtitle"><span class="permalink"><a href="#abed3177ba5248ce1d88a8e5b1b0975ce">&#9670;&nbsp;</a></span>RSTSR</h2>

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<p>RCC reset status register, Address offset: 0x01C </p>

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<a id="a8236e69f493fa3a1c13555582d192f59"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a8236e69f493fa3a1c13555582d192f59">&#9670;&nbsp;</a></span>RTCRST</h2>

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<p>RCC rtc control register, Address offset: 0x048 </p>

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<a id="a6f9f4322896705ef70941b053c088d4a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6f9f4322896705ef70941b053c088d4a">&#9670;&nbsp;</a></span>STICKCR</h2>

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<p>RCC systick timer circle adjust register, Address offset: 0x03C </p>

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<a id="a5e0fc1e67a356cb5e87b730518224671"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a5e0fc1e67a356cb5e87b730518224671">&#9670;&nbsp;</a></span>SWDIOCR</h2>

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<p>RCC endpoint function select register, Address offset: 0x040 </p>

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<a id="a21de9f48a3a96c231b7b2a586c49629d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a21de9f48a3a96c231b7b2a586c49629d">&#9670;&nbsp;</a></span>SYSCLKCR</h2>

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<p>RCC clk setting register, Address offset: 0x020 </p>

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<a id="a9a0654b081dfb1357231d309ee26acd1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a9a0654b081dfb1357231d309ee26acd1">&#9670;&nbsp;</a></span>SYSCLKSEL</h2>

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<p>RCC system clock select register, Address offset: 0x024 </p>

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<a id="ab1eca7a712b7385dea198c0e89087ca9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ab1eca7a712b7385dea198c0e89087ca9">&#9670;&nbsp;</a></span>UNLOCK</h2>

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<p>RCC register protect register, Address offset: 0x060 </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li><a class="el" href="wb32l003_8h_source.html">wb32l003.h</a></li>
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